Comments: Logic-timing simulation and the degradation delay model /

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Bibliographic Details
Main Author:	Bellido, Manuel J., 1964-
Other Authors:	Juan Chico, Jorge., Valencia, Manuel.
Format:	Book
Language:	English
Published:	London : Imperial College Press, c2006.
Subjects:	Timing circuits. Integrated circuits > Very large scale integration. Metal oxide semiconductors, Complementary.
Online Access:	Table of contents only
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