Logic-timing simulation and the degradation delay model /
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Main Author: | |
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Other Authors: | , |
Format: | Book |
Language: | English |
Published: |
London :
Imperial College Press,
c2006.
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Subjects: | |
Online Access: | Table of contents only |
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008 | 201225s2006 enka b 001 | eng d | ||
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020 | |a 9781860945892 (hb) | ||
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041 | |a eng | ||
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082 | 0 | 4 | |a 003.3 |2 23 |b L427-I 2006 |
100 | 1 | |a Bellido, Manuel J., |d 1964- | |
245 | 1 | 0 | |a Logic-timing simulation and the degradation delay model / |c Manuel J. Bellido, Jorge Juan, Manuel Valencia. |
260 | |a London : |b Imperial College Press, |c c2006. | ||
300 | |a xvii, 267 p. : |b ill. ; |c 24 cm. | ||
650 | 0 | |a Timing circuits. | |
650 | 0 | |a Integrated circuits |x Very large scale integration. | |
650 | 0 | |a Metal oxide semiconductors, Complementary. | |
700 | 1 | |a Juan Chico, Jorge. | |
700 | 1 | |a Valencia, Manuel. | |
856 | 4 | 1 | |3 Table of contents only |u http://www.loc.gov/catdir/toc/fy0705/2007271541.html |
942 | |2 ddc |c SACH | ||
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